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4, 8 meg x 64 dram sodimms micron technology, inc., reserves the right to change products or specifications without notice. dm83.p65 ? rev. 2/99 ?1999, micron technology, inc. 1 4, 8 meg x 64 dram sodimms small-outline dram module features ? jedec pinout in a 144-pin, small-outline, dual in- line memory module (sodimm) 32mb (4 meg x 64) and 64mb (8 meg x 64) high-performance cmos silicon-gate process single +3.3v 0.3v power supply all inputs, outputs and clocks are ttl-compatible 4,096-cycle cas#-before-ras# (cbr) refresh distributed across 64ms fast page mode (fpm) or extended data-out (edo) page mode access cycles optional self refresh mode (s) serial presence-detect (spd) options marking package 144-pin sodimm (gold) g timing 50ns access -5 60ns access -6 access cycles fast page mode none edo page mode x refresh rates standard refresh none self refresh (128ms period) s * *contact factory for availability mt4ldt464h (x)(s), mt8ldt864h (x)(s) for the latest data sheet, please refer to the micron web site: www.micronsemi.com/datasheets/datasheet.html pin assignment (front view) 144-pin small-outline dimm (i-1; 32mb) (i-2; 64mb) pin front pin back pin front pin back 1v ss 2v ss 73 oe# 74 r f u 3 dq0 4 dq32 75 v ss 76 v ss 5 dq1 6 dq33 77 rsvd 78 rsvd 7 dq2 8 dq34 79 rsvd 80 rsvd 9 dq3 10 dq35 81 v dd 82 v dd 11 v dd 12 v dd 83 dq16 84 dq48 13 dq4 14 dq36 85 dq17 86 dq49 15 dq5 16 dq37 87 dq18 88 dq50 17 dq6 18 dq38 89 dq19 90 dq51 19 dq7 20 dq39 91 v ss 92 v ss 21 v ss 22 v ss 93 dq20 94 dq52 23 cas0# 24 cas4# 95 dq21 96 dq53 25 cas1# 26 cas5# 97 dq22 98 dq54 27 v dd 28 v dd 99 dq23 100 dq55 29 a0 30 a3 101 v dd 102 v dd 31 a1 32 a4 103 a6 104 a7 33 a2 34 a5 105 a8 106 a11 35 v ss 36 v ss 107 v ss 108 v ss 37 dq8 38 dq40 109 a9 110 nc (a12) 39 dq9 40 dq41 111 a10 112 nc (a13) 41 dq10 42 dq42 113 v dd 114 v dd 43 dq11 44 dq43 115 cas2# 116 cas6# 45 v dd 46 v dd 117 cas3# 118 cas7# 47 dq12 48 dq44 119 v ss 120 v ss 49 dq13 50 dq45 121 dq24 122 dq56 51 dq14 52 dq46 123 dq25 124 dq57 53 dq15 54 dq47 125 dq26 126 dq58 55 v ss 56 v ss 127 dq27 128 dq59 57 rsvd 58 rsvd 129 v dd 130 v dd 59 rsvd 60 rsvd 131 dq28 132 dq60 61 rfu 62 rfu 133 dq29 134 dq61 63 v dd 64 v dd 135 dq30 136 dq62 65 rfu 66 rfu 137 dq31 138 dq63 67 we# 68 r f u 139 v ss 140 v ss 69 ras0# 70 nc 141 sda 142 scl 71 n c 72 n c 143 v dd 144 v dd note: symbols in parentheses are not used on these modules but may be used for other modules in this product family. they are for reference only. key timing parameters fpm operating mode speed t rc t rac t pc t aa t cac t rp -5 90ns 50ns 30ns 25ns 13ns 30ns -6 110ns 60ns 35ns 30ns 15ns 40ns edo operating mode speed t rc t rac t pc t aa t cac t cas -5 84ns 50ns 20ns 25ns 13ns 8ns -6 104ns 60ns 25ns 30ns 15ns 10ns
4, 8 meg x 64 dram sodimms micron technology, inc., reserves the right to change products or specifications without notice. dm83.p65 ? rev. 2/99 ?1999, micron technology, inc. 2 4, 8 meg x 64 dram sodimms cas#. additional columns may be accessed by provid- ing valid column addresses, strobing cas# and hold- ing ras# low, thus executing faster memory cycles. returning ras# high terminates the fast-page- mode operation. edo page mode edo page mode, designated by the ?x? option, is an accelerated fast-page-mode cycle. the pri- mary advantage of edo is the availability of data-out even after cas# goes back high. edo provides for cas# precharge time ( t cp) to occur without the out- put data going invalid. this elimination of cas# output control provides for pipelined reads. fast-page-mode modules have traditionally turned the output buffers off (high-z) with the rising edge of cas#. edo operates as any dram read or fast-page-mode read, except data will be held valid after cas# goes high, as long as ras# and oe# are held low and we# is held high. (refer to the 8 meg x 8 edo dram data sheet for additional infor- mation on edo functionality.) refresh memory cell data is retained in its correct state by maintaining power and executing any ras# cycle (read, write) or ras# refresh cycle (ras#-only, cbr or hidden) so that all combinations of ras# addresses are executed at least every t ref, regardless of sequence. the cbr refresh cycle will invoke the internal refresh counter for automatic ras# address- ing. an optional self refresh mode is also available on the ?s? version. the ?s? option allows the user the choice of a fully static, low-power data retention mode or a dynamic refresh mode at the extended refresh period of 128ms, or 125s per row when using distrib- uted cbr refesh. the optional self refresh feature is initiated by performing a cbr refresh cycle and holding ras# low for the specified t rass. the self refresh mode is terminated by driving ras# high for a minimum time of t rps. this delay allows for the completion of any internal refresh cycles that may be in process at the time of the ras# low-to- high transition. if the dram controller uses a distrib- uted refresh sequence, a burst refresh is not required upon exiting self refresh. however, if the dram con- troller utilizes a ras#-only or burst refresh sequence, all 1,240 rows must be refreshed within the average internal refresh rate, prior to the resumption of normal operation. part numbers fpm operating mode part number configuration refresh mt4ldt464hg-x 4 meg x 64 standard mt4ldt464hg-x s 4 meg x 64 self mt8ldt864hg-x 8 meg x 64 standard mt8ldt864hg-x s 8 meg x 64 self x = speed edo operating mode part number configuration refresh mt4ldt464hg-x x 4 meg x 64 standard mt4ldt464hg-x xs 4 meg x 64 self mt8ldt864hg-x x 8 meg x 64 standard mt8ldt864hg-x xs 8 meg x 64 self x = speed general description the mt4ldt464h (x)(s) and mt8ldt864h (x)(s) are randomly accessed 32mb and 64mb memories organized in a small-outline, x64 configuration. they are specially processed to operate from 3v to 3.6v for low-voltage memory systems. during read or write cycles, each location is uniquely addressed via the address bits. the row ad- dress is latched by the ras# signal, then the column address is latched by the cas# signal. read and write cycles are selected with the we# input. a logic high on we# dictates read mode, while a logic low on we# dictates write mode. during a write cycle, data-in (d) is latched by the falling edge of we# or cas#, whichever occurs last. an early write occurs when we# is taken low prior to cas# falling. a late write or read-modify-write oc- curs when we# falls after cas# is taken low. during early write cycles, the data outputs (q) will remain high-z, regardless of the state of oe#. during late write or read-modify-write cycles, oe# must be taken high to disable the data outputs prior to apply- ing input data. if a late write or read-modify- write is attempted while keeping oe# low, no write will occur, and the data outputs will drive read data from the access location. fast page mode fast-page-mode operations allow faster data operations (read or write) within a row-address- defined page boundary. the fast-page-mode cycle is always initiated with a row address strobed in by ras#, followed by a column address strobed in by
4, 8 meg x 64 dram sodimms micron technology, inc., reserves the right to change products or specifications without notice. dm83.p65 ? rev. 2/99 ?1999, micron technology, inc. 3 4, 8 meg x 64 dram sodimms we# oe# ras# casl# cash# dq0-dq15 u1 a0 e a11 we# oe# ras# casl# cash# a0 e a11 we# oe# ras# casl# cash# a0 e a11 we# oe# ras# casl# cash# a0 e a11 u1-u4 = mt4lc4m16r6 edo page mode u1-u4 = mt4lc4m16f5 fast page mode 12 oe# cas1# cas2# cas3# we# cas0# cas5# cas6# cas7# cas4# a0-a11 ras0# 16 dq0-dq15 dq16-dq31 dq0-dq15 u2 12 16 dq0-dq15 u3 12 16 dq32-dq47 dq48-dq63 dq0-dq15 u4 12 16 sa0 spd scl sda sa1 sa2 v dd v ss u1-u4 u1-u4 functional block diagram mt4ldt464h (x) (32mb)
4, 8 meg x 64 dram sodimms micron technology, inc., reserves the right to change products or specifications without notice. dm83.p65 ? rev. 2/99 ?1999, micron technology, inc. 4 4, 8 meg x 64 dram sodimms functional block diagram mt8ldt864h (x) (64mb) we# oe# ras# cas# u1 a0 e a11 we# oe# ras# cas# a0 e a11 we# oe# ras# cas# a0 e a11 we# oe# ras# cas# a0 e a11 we# oe# ras# cas# we# oe# ras# cas# we# oe# ras# cas# we# oe# ras# cas# u1-u8 = mt4lc8m8b6 fast page mode u1-u8 = mt4lc8m8c2 edo page mode 12 oe# cas1# cas2# cas3# we# cas0# cas5# cas6# cas7# cas4# a0-a11 ras0# 8 dq0-dq7 dq8-dq15 u2 12 8 u5 8 dq32-dq39 dq40-dq47 u6 8 u3 12 8 dq16-dq23 dq24-dq31 u4 12 a0 e a11 a0 e a11 a0 e a11 a0 e a11 12 12 12 12 8 u7 8 dq48-dq55 dq56-dq63 dq0-dq7 dq0-dq7 dq0-dq7 dq0-dq7 dq0-dq7 dq0-dq7 dq0-dq7 dq0-dq7 u8 8 sa0 spd scl sda sa1 sa2 v dd v ss u1-u8 u1-u8
4, 8 meg x 64 dram sodimms micron technology, inc., reserves the right to change products or specifications without notice. dm83.p65 ? rev. 2/99 ?1999, micron technology, inc. 5 4, 8 meg x 64 dram sodimms standby returning ras# and cas# high terminates a memory cycle and decreases chip current to a reduced standby level. also, the chip is preconditioned for the next cycle during the ras# high time. serial presence-detect operation this module family incorporates serial presence- detect (spd). the spd function is implemented using a 2,048-bit eeprom. this nonvolatile storage device contains 256 bytes. the first 128 bytes can be pro- grammed by micron to identify the module type and various dram organizations and timing parameters. the remaining 128 bytes of storage are available for use by the customer. system read/write operations be- tween the master (system logic) and the slave eeprom device (dimm) occur via a standard iic bus using the dimm?s scl (clock) and sda (data) signals. spd clock and data conventions data states on the sda line can change only during scl low. sda state changes during scl high are reserved for indicating start and stop conditions (fig- ures 1 and 2). spd start condition all commands are preceded by the start condition, which is a high-to-low transition of sda when scl is high. the spd device continuously monitors the sda and scl lines for the start condition and will not respond to any command until this condition has been met. spd stop condition all communications are terminated by a stop con- dition, which is a low-to-high transition of sda when scl is high. the stop condition is also used to place the spd device into standby power mode. spd acknowledge acknowledge is a software convention used to indicate successful data transfers. the transmitting device, either master or slave, will release the bus after transmitting eight bits. during the ninth clock cycle, the receiver will pull the sda line low to acknowledge that it received the eight bits of data (figure 3). the spd device will always respond with an ac- knowledge after recognition of a start condition and its slave address. if both the device and a write figure 3 acknowledge response from receiver scl from master data output from transmitter data output from receiver 9 8 acknowledge figure 2 definition of start and stop scl sda start bit stop bit figure 1 data validity scl sda data stable data stable data change
4, 8 meg x 64 dram sodimms micron technology, inc., reserves the right to change products or specifications without notice. dm83.p65 ? rev. 2/99 ?1999, micron technology, inc. 6 4, 8 meg x 64 dram sodimms operation have been selected, the spd device will re- spond with an acknowledge after the receipt of each subsequent eight-bit word. in the read mode the spd device will transmit eight bits of data, release the sda line and monitor the line for an acknowledge. if an acknowledge is detected and no stop condition is generated by the master, the slave will continue to transmit data. if an acknowledge is not detected, the slave will terminate further data transmissions and await the stop condition to return to standby power mode.
4, 8 meg x 64 dram sodimms micron technology, inc., reserves the right to change products or specifications without notice. dm83.p65 ? rev. 2/99 ?1999, micron technology, inc. 7 4, 8 meg x 64 dram sodimms serial presence-detect matrix byte description entry (version) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hex 0 number of bytes used by micron 128 1000000080 1 total number of spd memory bytes 256 0000100008 2 memory type fast page mode 0000000101 edo page mode 0000001002 3 number of row addresses 12 000011000c 4 number of column addresses 10 (32mb) 000010100a 11 (64mb) 000010110b 5 number of banks 1 0000000101 6 module data width 64 0100000040 7 module data width (continued) 0 0000000000 8 module voltage interface levels lvttl 0000000101 9 ras# access time ( t rac) 50ns (-5) 0011001032 60ns (-6) 001111003c 10 cas# access time ( t cac) 13ns (-5) 000011010d 15ns (-6) 000011110f 11 module configuration type nonparity 0000000000 12 refresh rate/type 15.6s/normal 0 000000000 2x - 31.25s/self 1000001103 13 dram width (primary dram) x16 (32mb) 0001000010 x8 (64mb) 0000100008 14 error checking dram data width none 0000000000 15-61 reserved 0000000000 62 spd revision rev. 0 0000000000 63 checksum for bytes 0-62 32mb -5 (edo) 0011000131 32mb -6 (edo) 001111013d 32mb -5 (fpm) 0011000030 32mb -6 (fpm) 001111003c 64mb -5 (edo) 001010102a 64mb -6 (edo) 0011011036 64mb -5 (fpm) 0010100129 64mb -6 (fpm) 0011010135 64 manufacturer ? s jedec id code mi cron 001011002c 65-71 manufacturer ? s jedec code (cont.) 11111111ff 72 manufacturing location 0000000101 0000001002 0000001103 0000010004 73-90 module part number (ascii) xxxxxxxxxx 91 pcb identification code 1 0000000101 2 0000001002 3 0000001103 4 0000010004 92 identification code (cont.) 0 0000000000 93 year of manufacture in bcd xxxxxxxxxx 94 week of manufacture in bcd xxxxxxxxxx 95-98 module serial number xxxxxxxxxx 99-125 manufacture specific data (rsvd) ????????? note: 1. ? 1 ? / ? 0 ? : serial data, ? driven to high ? / ? driven to low. ? 2. x = variable data.
4, 8 meg x 64 dram sodimms micron technology, inc., reserves the right to change products or specifications without notice. dm83.p65 ? rev. 2/99 ?1999, micron technology, inc. 8 4, 8 meg x 64 dram sodimms dc electrical characteristics and operating conditions (notes: 1) (v dd = +3.3v 0.3v) parameter/condition symbol min max units notes supply voltage v dd 3 3.6 v input high voltage: logic 1; all inputs v ih 2v dd + 0.3 v 30 input low voltage: logic 0; all inputs v il -0.5 0.8 v 30 input leakage current: ras0# i i 1 -16 16 a 23 any input 0v v in v dd + 0.3v a0-a11, we#, oe# i i 2 -16 16 a 23 (all other pins not under test = 0v) cas0#-cas7# i i 3 -2 2 a output leakage current: dq0-dq63 i oz -10 10 a dq is disabled; 0v v out v dd + 0.3v output levels: v oh 2.4 ? v output high voltage (i out = -2ma) output low voltage (i out = 2ma) v ol ? 0.4 v absolute maximum ratings* voltage on v dd supply relative to v ss ..................................... -1v to +4.6v voltage on inputs or i/o pins relative to v ss ................................. -1v to +4.6v operating temperature, t a (ambient) .. 0c to +70c storage temperature (plastic) ........... -55c to +125c power dissipation (32mb) ..................................... 4w power dissipation (64mb) ..................................... 8w *stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other condi- tions above those indicated in the operational sections of this specification is not implied. exposure to abso- lute maximum rating conditions for extended periods may affect reliability.
4, 8 meg x 64 dram sodimms micron technology, inc., reserves the right to change products or specifications without notice. dm83.p65 ? rev. 2/99 ?1999, micron technology, inc. 9 4, 8 meg x 64 dram sodimms i cc operating conditions and maximum limits (notes: 1, 5, 6) (v dd = +3.3v 0.3v) parameter/condition symbol size -5 -6 units notes standby current: ttl i cc 1 32mb 4 4 ma (ras# = cas# = v ih ) 64mb 8 8 standby current: cmos i cc 2 32mb 2 2 ma 26 (ras# = cas# = v dd - 0.2v) 64mb 4 4 operating current: random read/write 32mb 700 660 ma 3, 22 average power supply current i cc 3 (ras#, cas#, address cycling: t rc = t rc [min]) 64mb 1400 1320 operating current: fast page mode average power supply current i cc 4 32mb 420 380 ma 3, 22 (ras# = v il , cas#, address cycling: t pc = t pc [min]; 64mb 840 760 t cp, t asc = 10ns) operating current: edo page mode 32mb 620 500 ma 3, 22 average power supply current i cc 5 (ras# = v il , cas#, address cycling: t pc = t pc [min]) (x only) 64mb 1200 1000 refresh current: ras#-only 32mb 700 660 average power supply current i cc 6 ma 3, 22 (ras# cycling, cas# = v ih : t rc = t rc [min]) 64mb 1400 1320 refresh current: cbr 32mb 700 660 average power supply current i cc 7 ma 3, 4 (ras#, cas#, address cycling: t rc = t rc [min]) 64mb 880 800 refresh current: extended ( ? s ? version only) average power supply current: cas# = 0.2v or cbr cycling; i cc 8 32mb 1.6 1.6 ma 3, 4, 5 ras# = t ras (min); we# = v dd - 0.2v; a0-a11, 64mb 3.2 3.2 oe# and d in = v dd - 0.2v or 0.2v (d in may be left open) refresh current: self ( ? s ? version only) average power supply current: cbr with ras# i cc 9 32mb 1.6 1.6 ma 3, 4, 5 t rass (min) and cas# held low; we# = v dd - 0.2v; a0-a11, 64mb 2.4 2.4 oe# and d in = v dd - 0.2v or 0.2v (d in may be left open) max capacitance parameter symbol 32mb 64mb units notes input capacitance: a0-a11 c i 1 24 46 p f 2 input capacitance: we#, oe#, ras0# c i 2 32 62 p f 2 input capacitance: cas0#-cas7#, scl c i 3 10 10 p f 2 input/output capacitance: dq0-dq63 c io 1 10 18 p f 2 input/output capacitance: sda c io 2 10 10 p f 2 max
4, 8 meg x 64 dram sodimms micron technology, inc., reserves the right to change products or specifications without notice. dm83.p65 ? rev. 2/99 ?1999, micron technology, inc. 10 4, 8 meg x 64 dram sodimms fast page mode ac electrical characteristics (notes: 5, 6, 7, 8, 9, 12, 19) (v dd = +3.3v 0.3v) ac characteristics - fast page mode option -5 -6 parameter symbol miin max min max units notes access time from column address t aa 25 30 ns column-address hold time (referenced to ras#) t ar 40 45 ns column-address setup time t asc 0 0 ns row-address setup time t asr 0 0 ns column address to we# delay time t awd 48 55 ns 27 access time from cas# t cac 13 15 ns column-address hold time t cah 8 10 ns cas# pulse width t cas 13 10,000 15 10,000 ns cas# low to ? don ? t care ? during self refresh t chd 15 15 ns 27 cas# hold time (cbr refresh) t chr 15 15 ns 4 cas# to output in low-z t clz 3 3 ns 21 cas# precharge time t cp 8 10 ns 13 access time from cas# precharge t cpa 30 35 ns cas# to ras# precharge time t crp 5 5 ns cas# hold time t csh 50 60 ns cas# setup time (cbr refresh) t csr 5 5 ns cas# to we# delay time t cwd 36 40 ns 27 write command to cas# lead time t cwl 13 15 ns data-in hold time t dh 8 10 ns 18 data-in setup time t ds 0 0 ns 18 output disable t od 3 13 3 15 ns output enable t oe 13 15 ns oe# hold time from we# during t oeh 13 15 ns 28 read-modify-write cycle output buffer turn-off delay t off 3 13 3 15 ns 17, 24 oe# setup prior to ras# during t ord 0 0 ns hidden refresh cycle fast-page-mode read or write cycle time t pc 30 35 ns fast-page-mode read-write cycle time t prwc 76 85 ns access time from ras# t rac 50 60 ns ras# to column-address delay time t rad 13 15 ns 15 row-address hold time t rah 8 10 ns ras# pulse width t ras 50 10,000 60 10,000 ns ras# pulse width (fast page mode) t rasp 50 125,000 60 125,000 ns ras# pulse width during self refresh t rass 100 100 s
4, 8 meg x 64 dram sodimms micron technology, inc., reserves the right to change products or specifications without notice. dm83.p65 ? rev. 2/99 ?1999, micron technology, inc. 11 4, 8 meg x 64 dram sodimms fast page mode ac electrical characteristics (notes: 5, 6, 7, 8, 9, 12, 19) (v dd = +3.3v 0.3v) ac characteristics - fast page mode option -5 -6 parameter symbol min max min max units notes random read or write cycle time t rc 90 110 ns ras# to cas# delay time t rcd 18 20 ns 14 read command hold time (referenced to cas#) t rch 0 0 ns 16 read command setup time t rcs 0 0 ns refresh period (4,096 cycles) t ref 64 64 ms ras# precharge time t rp 30 40 ns ras# to cas# precharge time t rpc 0 0 ns ras# precharge time exiting self refresh t rps 90 105 ns read command hold time (referenced to ras#) t rrh 0 0 ns 16 ras# hold time t rsh 13 15 ns read-write cycle time t rwc 131 155 ns ras# to we# delay time t rwd 73 85 ns 27 write command to ras# lead time t rwl 13 15 ns transition time (rise or fall) t t250250ns write command hold time t wch 8 10 ns write command hold time (referenced to ras#) t wcr 40 45 ns we# command setup time t wcs 0 0 ns 27 write command pulse width t wp 8 10 ns we# hold time (cbr refresh) t wrh 10 10 ns we# setup time (cbr refresh) t wrp 10 10 ns
4, 8 meg x 64 dram sodimms micron technology, inc., reserves the right to change products or specifications without notice. dm83.p65 ? rev. 2/99 ?1999, micron technology, inc. 12 4, 8 meg x 64 dram sodimms edo page mode ac electrical characteristics (notes: 5, 6, 7, 8, 9, 12, 19) (v dd = +3.3v 0.3v) ac characteristics - edo page mode option -5 -6 parameter symbol min max min max units notes access time from column address t aa 25 30 ns column-address setup to cas# precharge t ach 12 15 ns column-address hold time (referenced to ras#) t ar 38 45 ns column-address setup time t asc 0 0 ns row-address setup time t asr 0 0 ns column address to we# delay time t awd 42 49 ns 27 access time from cas# t cac 13 15 ns column-address hold time t cah 8 10 ns cas# pulse width t cas 8 10,000 10 10,000 ns cas# low to ? don ? t care ? during self refresh t chd 15 15 ns cas# hold time (cbr refresh) t chr 8 10 ns 4 cas# to output in low-z t clz 0 0 ns data output hold after next cas# low t coh 3 3 ns cas# precharge time t cp 8 10 ns 13 access time from cas# precharge t cpa 28 35 ns cas# to ras# precharge time t crp 5 5 ns cas# hold time t csh 38 45 ns cas# setup time (cbr refresh) t csr 5 5 ns cas# to we# delay time t cwd 28 35 ns 27 write command to cas# lead time t cwl 8 10 ns data-in hold time t dh 8 10 ns 18 data-in setup time t ds 0 0 ns 18 output disable t od 0 12 0 15 ns output enable t oe 12 15 ns oe# hold time from we# during t oeh 8 10 ns 28 read-modify-write cycle oe# high hold from cas# high t oehc 5 10 ns 28 oe# high pulse width t oep 5 5 ns oe# low to cas# high setup time t oes 4 5 ns output buffer turn-off delay t off 0 12 0 15 ns 17, 24
4, 8 meg x 64 dram sodimms micron technology, inc., reserves the right to change products or specifications without notice. dm83.p65 ? rev. 2/99 ?1999, micron technology, inc. 13 4, 8 meg x 64 dram sodimms edo page mode ac electrical characteristics (notes: 5, 6, 7, 8, 9, 12, 19) (v dd = +3.3v 0.3v) ac characteristics - edo page mode option -5 -6 parameter symbol min max min max units notes oe# setup prior to ras# t ord 0 0 ns during hidden refresh cycle edo-page-mode read or write cycle time t pc 20 25 ns edo-page-mode read-write cycle time t prwc 47 56 ns access time from ras# t rac 50 60 ns ras# to column-address delay time t rad 9 12 ns 15 row-address hold time t rah 9 10 ns ras# pulse width t ras 50 10,000 60 10,000 ns ras# pulse width (edo page mode) t rasp 50 125,000 60 125,000 ns ras# pulse width during self refresh t rass 100 100 s random read or write cycle time t rc 84 104 ns ras# to cas# delay time t rcd 11 14 ns 14 read command hold time (referenced to cas#) t rch 0 0 ns 16 read command setup time t rcs 0 0 ns refresh period (4,096 cycles) t ref 64 64 ms ras# precharge time t rp 30 40 ns ras# to cas# precharge time t rpc 5 5 ns ras# precharge time exiting self refresh t rps 90 105 ns read command hold time (referenced to ras#) t rrh 0 0 ns 16 ras# hold time t rsh 13 15 ns read-write cycle time t rwc 116 140 ns ras# to we# delay time t rwd 67 79 ns 28 write command to ras# lead time t rwl 13 15 ns transition time (rise or fall) t t250250ns write command hold time t wch 8 10 ns write command hold time (referenced to ras#) t wcr 38 45 ns we# command setup time t wcs 0 0 ns 28 output disable delay from we# t whz 0 12 0 15 ns write command pulse width t wp 5 5 ns we# pulse to disable at cas# high t wpz 10 10 ns we# hold time (cbr refresh) t wrh 8 10 ns we# setup time (cbr refresh) t wrp 8 10 ns
4, 8 meg x 64 dram sodimms micron technology, inc., reserves the right to change products or specifications without notice. dm83.p65 ? rev. 2/99 ?1999, micron technology, inc. 14 4, 8 meg x 64 dram sodimms serial presence-detect eeprom ac electrical characteristics (notes: 1) (v dd = +3.3v 0.3v) parameter/condition symbol min max units notes scl low to sda data-out valid t aa 0.3 3.5 s time the bus must be free before a new transition can start t buf 4.7 s data-out hold time t dh 300 ns sda and scl fall time t f 300 ns data-in hold time t hd:dat 0 s start condition hold time t hd:sta 4 s clock high period t high 4 s noise suppression time constant at scl, sda inputs t i 100 ns clock low period t low 4.7 s sda and scl rise time t r1s scl clock frequency t scl 100 khz data-in setup time t su:dat 250 ns start condition setup time t su:sta 4.7 s stop condition setup time t su:sto 4.7 s write cycle time t wr 10 ms 29 serial presence-detect eeprom dc operating conditions (notes: 1) (v dd = +3.3v 0.3v) parameter/condition symbol min max units notes supply voltage v dd 3 3.6 v input high voltage: logic 1; all inputs v ih v dd x 0.7 v dd + 0.5 v input low voltage: logic 0; all inputs v il -1 v dd x 0.3 v output low voltage: i out = 3ma v ol ? 0.4 v input leakage current: v in = gnd to v dd i li ? 10 a output leakage current: v out = gnd to v dd i lo ? 10 a standby current: i sb ? 30 a scl = sda = v dd - 0.3v; all other inputs = gnd or 3.3v +10% power supply current: i cc ? 2ma scl clock frequency = 100 khz
4, 8 meg x 64 dram sodimms micron technology, inc., reserves the right to change products or specifications without notice. dm83.p65 ? rev. 2/99 ?1999, micron technology, inc. 15 4, 8 meg x 64 dram sodimms notes 1. all voltages referenced to v ss . 2. this parameter is sampled. v dd = +3.3v; f = 1 mhz. 3. i cc is dependent on output loading and cycle rates. specified values are obtained with minimum cycle time and the outputs open. 4. enables on-chip refresh and address counters. 5. the minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range is ensured. 6. an initial pause of 100s is required after power- up, followed by eight ras# refresh cycles (ras#-only or cbr with we# high), before proper device operation is ensured. the eight ras# cycle wake-ups should be repeated any time the t ref refresh requirement is exceeded. 7. ac characteristics assume t t = 5ns for fpm and t t = 2.5ns for edo. 8. v ih (min) and v il (max) are reference levels for measuring timing of input signals. transition times are measured between v ih and v il (or between v il and v ih ). 9. in addition to meeting the transition rate specification, all input signals must transit between v ih and v il (or between v il and v ih ) in a mono- tonic manner. 10.if cas# = v ih , data output is high-z. 11.if cas# = v il , data output may contain data from the last valid read cycle. 12.measured with a load equivalent to two ttl gates and 100pf and v ol = 0.8v and v oh = 2v. 13.if cas# is low at the falling edge of ras#, q will be maintained from the previous cycle. to initiate a new cycle and clear the data-out buffer, cas# must be pulsed high for t cp. 14.the t rcd (max) limit is no longer specified. t rcd (max) was specified as a reference point only. if t rcd was greater than the specified t rcd (max) limit, then access time was controlled exclusively by t cac ( t rac [min] no longer applied). with or without the t rcd (max) limit, t aa and t cac must always be met. 15.the t rad (max) limit is no longer specified. t rad (max) was specified as a reference point only. if t rad was greater than the specified t rad (max) limit, then access time was controlled exclusively by t aa ( t rac and t cac no longer applied). with or without the t rad (max) limit, t aa, t rac and t cac must always be met. 16.either t rch or t rrh must be satisfied for a read cycle. 17. t off (max) defines the time at which the output achieves the open circuit condition and is not referenced to v oh or v ol . 18.these parameters are referenced to cas# leading edge in early write cycles and we# leading edge in late write or read-modify-write cycles. 19.if oe# is tied permanently low, late write or read-modify-write operations are not permissible and should not be attempted. additionally, with edo, we# must be pulsed during cas# high time in order to place i/o buffers in high-z. 20.a hidden refresh may also be performed after a write cycle. in this case, we# = low and oe# = high. 21.the 3ns minimum is a parameter guaranteed by design. 22.column address changed once each cycle. 23.8mb module values will be half of those shown. 24.with the fpm option, t off is determined by the first ras# or cas# signal to transition high. in comparison, t off on an edo option is deter- mined by the latter of the ras# and cas# signals to transition high. 25.applies to both fpm and edo operating modes. 26.all other inputs at 0.2v or v dd - 0.2v. 27. t wcs, t rwd, t awd and t cwd are not restrictive operating parameters. t wcs applies to early write cycles. t rwd, t awd and t cwd apply to read-modify-write cycles. if t wcs t wcs (min), the cycle is an early write cycle and the data output will remain an open circuit through- out the entire cycle. if t wcs < t wcs (min) and t rwd t rwd (min), t awd t awd (min) and t cwd t cwd (min), the cycle is a read- modify-write and the data output will contain data read from the selected cell. if neither of the above conditions is met, the state of data-out is indeterminate. oe# held high and we# taken low after cas# goes low result in a late write (oe#-controlled) cycle. t wcs, t rwd, t cwd and t awd are not applicable in a late write cycle.
4, 8 meg x 64 dram sodimms micron technology, inc., reserves the right to change products or specifications without notice. dm83.p65 ? rev. 2/99 ?1999, micron technology, inc. 16 4, 8 meg x 64 dram sodimms notes (continued) 2 8.late write and read-modify-write cycles must have both t od and t oeh met (oe# high during write cycle) in order to ensure that the output buffers will be open during the write cycle. the dqs will provide the previously read data if cas# remains low and oe# is taken back low after t oeh is met. if cas# goes high prior to oe# going back low, the dqs will remain open. 29.the spd eeprom write cycle time ( t wr) is the time from a valid stop condition of a write sequence to the end of the eeprom internal erase/ program cycle. during the write cycle, the eeprom bus interface circuit is disabled, sda remains high due to pull-up resistor, and the eeprom does not respond to its slave address. 30.v ih overshoot: v ih (max) = v dd + 2v for a pulse width 10ns, and the pulse width cannot be greater than one third of the cycle rate. v il undershoot: v il (min) = -2v for a pulse width 10ns, and the pulse width cannot be greater than one third of the cycle rate.
4, 8 meg x 64 dram sodimms micron technology, inc., reserves the right to change products or specifications without notice. dm83.p65 ? rev. 2/99 ?1999, micron technology, inc. 17 4, 8 meg x 64 dram sodimms read cycle 25 t rrh t clz t cac t rac t aa valid data open t off t rch row t rcs t asc t rah t rad t ar t cah t rcd t cas t rsh t csh t rp t rc t ras t crp t asr row open ras# v v ih il v v ih il addr v v ih il dq v v oh ol v v ih il t od t oe oe# v v ih il column we# casl#/cash# note 1 t ach don ? t care undefined note: 1. for edo, t off is referenced from rising edge of ras# or cas#, whichever occurs last. for fpm, t off is referenced from rising edge of ras# or cas#, whichever occurs first. fast page mode and edo page mode timing parameters -5 -6 symbol min max min max units t a a 25 30 n s t ach (edo) 12 15 ns t ar (edo) 38 45 ns t asc 0 0 ns t asr 0 0 ns t c a c 13 15 n s t ar (fpm) 40 45 ns t cah 8 10 ns t cas (edo) 8 10,000 10 10,000 ns t cas (fpm) 13 10,000 15 10,000 ns t clz (edo) 0 0 ns t clz (fpm) 3 3 ns t crp 5 5 ns t csh (edo) 38 45 ns t csh (fpm) 50 60 ns t od (edo) 0 12 0 15 ns t od (fpm) 3 13 3 15 ns t oe (edo) 12 15 ns -5 -6 symbol min max min max units t oe (fpm) 13 15 ns t off (edo) 0 12 0 15 ns t off (fpm) 3 13 3 15 ns t r a c 50 60 n s t rad (edo) 9 12 ns t rad (fpm) 13 15 ns t rah (edo) 9 10 ns t rah (fpm) 8 10 ns t ras 50 10,000 60 10,000 ns t rc (edo) 84 104 ns t rc (fpm) 90 110 ns t rcd (edo) 11 14 ns t rcd (fpm) 18 20 ns t rch 0 0 ns t rcs 0 0 ns t rp 30 40 n s t rrh 0 0 ns t rsh1315ns
4, 8 meg x 64 dram sodimms micron technology, inc., reserves the right to change products or specifications without notice. dm83.p65 ? rev. 2/99 ?1999, micron technology, inc. 18 4, 8 meg x 64 dram sodimms fast page mode and edo page mode timing parameters -5 -6 symbol min max min max units t ach (edo) 12 15 ns t ar (edo) 38 45 ns t ar (fpm) 40 45 ns t asc 0 0 ns t asr 0 0 ns t cah 8 10 ns t cas (fpm) 13 10,000 15 10,000 ns t cas (edo) 8 10,000 10 10,000 ns t crp 5 5 ns t csh (fpm) 50 60 ns t csh (edo) 38 45 ns t cwl (fpm) 13 15 ns t cwl (edo) 8 10 ns t dh 8 10 ns t ds 0 0 ns t rad (fpm) ? 15 n s t rad (edo) 9 12 ns early write cycle 25 don ? t care undefined v v ih il valid data row column row t ds t wp t wch t wcs t wcr t rwl t cwl t cah t asc t rah t asr t rad t ar t cas t rsh t csh t rcd t crp t ras t rc t rp v v ih il addr v v ih il v v ih il dq v v ioh iol v v ih il ras# oe# t dh we# casl#/cash# t ach -5 -6 symbol min max min max units t rah (edo) 9 10 ns t rah (fpm) 8 10 ns t ras 50 10,000 60 10,000 ns t rc (fpm) 90 110 ns t rc (edo) 84 104 ns t rcd (fpm) 18 20 ns t rcd (edo) 11 14 ns t rp 30 40 n s t rsh1315ns t rwl 13 15 n s t wch 8 10 ns t wcr (edo) 38 45 ns t wcr (fpm) 40 45 ns t wcs 0 0 ns t wp (fpm) 8 10 ns t wp (edo) 5 5 ns
4, 8 meg x 64 dram sodimms micron technology, inc., reserves the right to change products or specifications without notice. dm83.p65 ? rev. 2/99 ?1999, micron technology, inc. 19 4, 8 meg x 64 dram sodimms fast page mode timing parameters -5 -6 symbol min max min max units t a a 25 30 n s t ar 40 5 ns t asc 0 0 ns t asr 0 0 ns t c a c 13 15 n s t cah 8 10 ns t cas 13 10,000 15 10,000 ns t clz 3 3 ns t cp 8 10 ns t cpa 30 35 n s t crp 5 5 ns t c s h 50 60 n s t od 3 13 3 15 ns valid data valid data valid data column column column row row don ? t care undefined t rcs t cah t asc t cp t rsh t cp t cp t cas t rcd t crp t pc t csh t rasp t rp t cah t asc t cah t asc t ar t rah t rad t asr t rcs t rch t rch t rcs t rrh t rch t off t cac t cpa t aa t clz t off t cac t cpa t aa t clz t off t cac t rac t aa t clz t oe t od t oe t od t oe t od open open v v ih il v v ih il addr v v ih il v v ih il dq v v ioh iol v v ih il ras# oe# t cas t cas we# casl#/cash# fast-page-mode read cycle -5 -6 symbol min max min max units t oe 13 15 n s t off 3 13 3 15 ns t pc 30 35 n s t r a c 50 60 n s t r a d 13 15 n s t rah 8 10 ns t rasp 50 125,000 60 125,000 ns t r c d 18 20 n s t rch 0 0 ns t rcs 0 0 ns t rp 30 40 n s t rrh 0 0 ns t rsh1315ns
4, 8 meg x 64 dram sodimms micron technology, inc., reserves the right to change products or specifications without notice. dm83.p65 ? rev. 2/99 ?1999, micron technology, inc. 20 4, 8 meg x 64 dram sodimms edo-page-mode read cycle we# ach valid data valid data valid data column column column row row don ? t care undefined t od t cah t asc t cp t rsh t cp t cp t cas t rcd t crp t pc t csh t rasp t rp t cah t asc t cah t asc t rad t ar t rah t rad t asr t rcs t rrh t rch t off t cac t cpa t aa t clz t cac t cpa t aa t cac t rac t aa t clz t oe t od t oe t od open open v v ih il v v ih il addr v v ih il v v ih il dq v v oh ol v v ih il ras# oe# casl#/cash# t coh t oep t oehc t oes t oes t cas t cas t ach t ach t edo page mode timing parameters -5 -6 symbol min max min max units t a a 25 30 n s t a c h 12 15 n s t ar 38 45 n s t asc 0 0 ns t asr 0 0 ns t c a c 13 15 n s t cah 8 10 ns t cas 8 10,000 10 10,000 ns t clz 0 0 ns t coh 3 3 ns t cp 8 10 ns t cpa 28 35 n s t crp 5 5 ns t c s h 38 45 n s t od 0 12 0 15 ns t oe 12 15 n s t oehc 5 10 ns t oep 5 5 ns t oes 4 5 ns t off 0 12 0 15 ns t pc 20 25 n s t r a c 50 60 n s t rad 9 12 ns t rah 9 10 ns t rasp 50 125,000 60 125,000 ns t r c d 11 14 n s t rch 0 0 ns t rcs 0 0 ns t rp 30 40 n s t rrh 0 0 ns t rsh1315ns -5 -6 symbol min max min max units
4, 8 meg x 64 dram sodimms micron technology, inc., reserves the right to change products or specifications without notice. dm83.p65 ? rev. 2/99 ?1999, micron technology, inc. 21 4, 8 meg x 64 dram sodimms fast page mode and edo page mode timing parameters -5 -6 symbol min max min max units t ach (edo) 12 15 ns t ar (edo) 38 45 ns t ar (fpm) 40 45 ns t asc 0 0 ns t asr 0 0 ns t cah 8 10 ns t cas (edo) 8 10,000 10 10,000 ns t cas (fpm) 13 10,000 15 10,000 ns t cp 8 10 ns t crp 5 5 ns t csh (edo) 38 45 ns t csh (fpm) 50 60 ns t cwl (edo) 8 10 ns t cwl (fpm) 13 15 ns t dh 8 10 ns t ds 0 0 ns t pc (edo) 20 25 ns t pc (fpm) 30 35 ns t rad (edo) 9 12 ns t rad (fpm) 13 15 ns t rah (edo) 9 10 ns t rah (fpm) 9 10 ns t rasp 50 125,000 60 125,000 ns t rcd (edo) 11 14 ns t rcd (fpm) 18 20 ns t rp 30 40 n s t rsh1315ns t rwl 13 15 n s t wch 8 10 ns t wcr (edo) 38 45 ns t wcr (fpm) 38 45 ns t wcs 0 0 ns t wp (edo) 5 5 ns t wp (fpm) 8 10 ns fast/edo-page-mode early write cycle 25 t ds t dh t ds t dh t ds t dh t wcr valid data valid data valid data t rwl t wp t cwl t wch t wcs t wp t cwl t wch t wcs t wp t cwl t wch t wcs t cah t asc t cah t asc t cah t asc t rah t asr t rad t ar column column column row row t cp t rsh t cp t cp t cas t rcd t crp t pc t csh t rasp t rp v v ih il casl#/cash# v v ih il addr v v ih il we# v v ih il dq v v ioh iol ras# oe# v v ih il don ? t care undefined t t ach t ach t cas t cas ach -5 -6 symbol min max min max units
4, 8 meg x 64 dram sodimms micron technology, inc., reserves the right to change products or specifications without notice. dm83.p65 ? rev. 2/99 ?1999, micron technology, inc. 22 4, 8 meg x 64 dram sodimms read-write cycle 25 (late write and read-modify-write cycles) valid d out valid d in row column row v v ih il v v ih il addr v v ih il v v ih il dq v v ioh iol v v ih il ras# open open t oe t od t cac t rac t aa t clz t ds t dh t awd t wp t rwl t cwl t cwd t rwd t rcs t asc t cah t ar t asr t rad t crp t rcd t cas t rsh t csh t ras t rwc t rp t rah oe# t oeh we# t ach cas# don ? t care undefined t od (edo) 0 12 0 15 ns t od (fpm) 3 13 3 15 ns t oe (edo) 12 15 ns t oeh (edo) 8 10 ns t oeh (fpm) 13 15 ns t r a c 50 60 n s t rad (edo) 9 12 ns t rad (fpm) 13 15 ns t rah (edo) 9 10 ns t rah (fpm) 8 10 ns t ras 50 10,000 60 10,000 ns t rcd (edo) 11 14 ns t rcd (fpm) 18 20 ns t rcs 0 0 ns t rp 30 40 n s t rsh1315ns t rwc (edo) 116 140 ns t rwc (fpm) 131 155 ns t rwd (edo) 67 79 ns t rwd (fpm) 73 85 ns t rwl 13 15 n s t wp (edo) 5 5 ns t wp (fpm) 8 10 ns fast page mode and edo page mode timing parameters -5 -6 symbol min max min max units t a a 25 30 n s t ach (edo) 12 15 ns t ar (edo) 38 45 ns t ar (fpm) 40 45 ns t asc 0 0 ns t asr 0 0 ns t awd (edo) 42 49 ns t awd (fpm) 48 55 ns t c a c 13 15 n s t cah 8 10 ns t cas (edo) 8 10,000 10 10,000 ns t cas (fpm) 13 10,000 15 10,000 ns t clz (edo) 0 0 ns t clz (fpm) 3 3 ns t crp 5 5 ns t csh (edo) 38 45 ns t csh (fpm) 50 60 ns t cwd (edo) 28 35 ns t cwd (fpm) 36 40 ns t cwl (edo) 8 10 ns t cwl (fpm) 13 15 ns t dh 8 10 ns t ds 0 0 ns -5 -6 symbol min max min max units
4, 8 meg x 64 dram sodimms micron technology, inc., reserves the right to change products or specifications without notice. dm83.p65 ? rev. 2/99 ?1999, micron technology, inc. 23 4, 8 meg x 64 dram sodimms fast/edo-page-mode read-write cycle 25 (late write and read-modify-write cycles) don ? t care undefined t t od t oe t od t oe t od t oe open d out valid d out valid d out valid d in valid d in valid d in valid open t dh t ds t aa t cpa t clz t cac t dh t ds t aa t cpa t clz t cac t dh t ds t aa t clz t cac t rac t wp t cwl t rwl t cwd t awd t wp t cwl t cwd t awd t wp t cwl t cwd t awd t rcs t rwd t asr t rah t asc t rad t ar t cah t asc t cah t asc t cah t cp t rsh t cp t rp t rasp t cp t rcd t csh t pc t crp row column column column row v v ih il v v ih il addr v v ih il v v ih il dq v v ioh iol v v ih il ras# oe# t prwc oeh t cas t cas t cas we# casl#/cash# note 1 note: 1. t pc is for late write cycles only. t od (edo) 0 12 0 15 ns t od (fpm) 3 13 3 15 ns t oe (edo) 12 15 ns t oe (fpm) 13 15 ns t oeh (edo) 8 10 ns t oeh (fpm) 13 15 ns t pc (edo) 20 25 ns t pc (fpm) 30 35 ns t prwc (edo) 47 56 ns t prwc (fpm) 76 85 ns t r a c 50 60 n s t rad (edo) 9 12 ns t rad (fpm) 13 15 ns t rah (edo) 9 10 ns t rah (fpm) 8 10 ns t rasp 50 125,000 60 125,000 ns t rcd (edo) 11 14 ns t rcd (fpm) 18 20 ns t rcs 0 0 ns t rp 30 40 n s t rsh1315ns t rwd (edo) 67 79 ns t rwd (fpm) 73 85 ns t rwl 13 15 n s t wp (edo) 5 5 ns t wp (fpm) 8 10 ns fast page mode and edo page mode timing parameters -5 -6 symbol min max min max units t a a 25 30 n s t ar (edo) 38 45 ns t ar (fpm) 40 45 ns t asc 0 0 ns t asr 0 0 ns t awd (edo) 42 49 ns t awd (fpm) 48 55 ns t c a c 13 15 n s t cah 8 10 ns t cas (edo) 8 10,000 10 10,000 ns t cas (fpm) 13 10,000 15 10,000 ns t clz (edo) 0 0 ns t clz (fpm) 3 3 ns t cp 8 10 ns t cpa (edo) 28 35 ns t cpa (fpm) 30 35 ns t crp 5 5 ns t csh (edo) 38 45 ns t csh (fpm) 50 60 ns t cwd (edo) 28 35 ns t cwd (fpm) 36 40 ns t cwl (edo) 8 10 ns t cwl (fpm) 13 15 ns t dh 8 10 ns t ds 0 0 ns -5 -6 symbol min max min max units
4, 8 meg x 64 dram sodimms micron technology, inc., reserves the right to change products or specifications without notice. dm83.p65 ? rev. 2/99 ?1999, micron technology, inc. 24 4, 8 meg x 64 dram sodimms v v ih il v v ih il ras# v v ih il addr v v ih il we# t rasp t rp row column (a) column (n) row v v ih il oe# v v ioh iol t crp t csh t cas t rcd t asr t rah t rad t asc t ar t cah t asc t cah t asc t cah t cp t rsh valid d in t rcs t rch t wcs t oe valid d out valid d out t whz t cac t cpa t aa t cac t aa open dq t pc rac t t coh t wch t ds t dh t pc column (b) t ach casl#/cash# t cas t cas t cp t cp don ? t care undefined edo-page-mode read early write cycle (pseudo read-modify-write) t oe 12 15 n s t pc 20 25 n s t r a c 50 60 n s t rad 9 12 ns t rah 9 10 ns t rasp 50 125,000 60 125,000 ns t r c d 11 14 n s t rch 0 0 ns t rcs 0 0 ns t rp 30 40 n s t rsh1315ns t wch 8 10 ns t wcs 0 0 ns t whz 0 12 0 15 ns -5 -6 symbol min max min max units edo page mode timing parameters -5 -6 symbol min max min max units t a a 25 30 n s t a c h 12 15 n s t ar 38 45 n s t asc 0 0 ns t asr 0 0 ns t c a c 13 15 n s t cah 8 10 ns t cas 8 10,000 10 10,000 ns t coh 3 3 ns t cp 8 10 ns t cpa 28 35 n s t crp 5 5 ns t c s h 38 45 n s t dh 8 10 ns t ds 0 0 ns
4, 8 meg x 64 dram sodimms micron technology, inc., reserves the right to change products or specifications without notice. dm83.p65 ? rev. 2/99 ?1999, micron technology, inc. 25 4, 8 meg x 64 dram sodimms fast page mode timing parameters -5 -6 symbol min max min max units t a a 25 30 n s t ar 40 45 n s t asc 0 0 ns t asr 0 0 ns t c a c 13 15 n s t cah 8 10 ns t cas 13 10,000 15 10,000 ns t clz 3 3 ns t cp 8 10 ns t crp 5 5 ns t c s h 50 60 n s t cwl 13 15 n s t dh 8 10 ns t ds 0 0 ns row valid data valid data open t crp t rcd t cas t rsh t rasp t rp t pc t asc t cah t ar t asr t rad t rah t wcs t wp t rwl t rcs t dh t ds t cac t off v v ih il casl#/cash# v v ih il addr v v ih il ras# q v v oh ol we# v v ih il t csh column t cp t cp t asc t cah t cwl t wch t clz t aa rac don ? t care undefined t note 1 oe# v v ih il row column t cas fast-page-mode read early write cycle (pseudo read-modify-write) note: 1. do not drive data prior to tristate. -5 -6 symbol min max min max units t off 3 13 3 15 ns t pc 30 35 n s t r a c 50 60 n s t r a d 13 15 n s t rah 8 10 ns t rasp 50 10,000 60 125,000 ns t r c d 18 20 n s t rcs 0 0 ns t rp 30 40 n s t rsh1315ns t rwl 13 15 n s t wch 8 10 ns t wcs 0 0 ns t wp 8 10 ns
4, 8 meg x 64 dram sodimms micron technology, inc., reserves the right to change products or specifications without notice. dm83.p65 ? rev. 2/99 ?1999, micron technology, inc. 26 4, 8 meg x 64 dram sodimms edo read cycle (with we#-controlled disable) t clz t cac t rac t aa valid data open t rch t rcs t asc t rah t rad t ar t cah t rcd t cas t csh t crp t asr row open ras# v v ih il v v ih il addr v v ih il dq v v oh ol v v ih il t od t oe oe# v v ih il column we# t whz t wpz t cp t asc t rcs column t clz casl#/cash# don ? t care undefined -5 -6 symbol min max min max units t od 0 12 0 15 ns t oe 12 15 n s t r a c 50 60 n s t rad 9 12 ns t rah 9 10 ns t r c d 11 14 n s t rch 0 0 ns t rcs 0 0 ns t whz 0 12 0 15 ns t wpz 10 10 n s edo page mode timing parameters -5 -6 symbol min max min max units t a a 25 30 n s t ar 38 45 n s t asc 0 0 ns t asr 0 0 ns t c a c 13 15 n s t cah 8 10 ns t cas 8 10,000 10 10,000 ns t clz 0 0 ns t cp 8 10 ns t crp 5 5 ns t c s h 38 45 n s
4, 8 meg x 64 dram sodimms micron technology, inc., reserves the right to change products or specifications without notice. dm83.p65 ? rev. 2/99 ?1999, micron technology, inc. 27 4, 8 meg x 64 dram sodimms t rc (fpm) 90 110 ns t rc (edo) 84 104 ns t rp 30 40 n s t rpc (fpm) 0 0 ns t rpc (edo) 5 5 ns ras#-only refresh cycle 25 row v v ih il cas# v v ih il addr v v ih il ras# t rc t ras t rp t crp t asr t rah row open dq v v oh ol t rpc we# v v ih il don ? t care undefined -5 -6 symbol min max min max units fast page mode and edo page mode timing parameters -5 -6 symbol min max min max units t asr 0 0 ns t crp 5 5 ns t rah (edo) 9 10 ns t rah (fpm) 8 10 ns t ras 50 10,000 60 10,000 ns
4, 8 meg x 64 dram sodimms micron technology, inc., reserves the right to change products or specifications without notice. dm83.p65 ? rev. 2/99 ?1999, micron technology, inc. 28 4, 8 meg x 64 dram sodimms fast page mode and edo page mode timing parameters -5 -6 symbol min max min max units t c h d 15 15 n s t chr (fpm) 15 15 ns t chr (edo) 8 10 ns t cp 8 10 ns t csr 5 5 ns t ras 50 10,000 60 10,000 ns t rass 100 100 s t rp 30 40 n s cbr refresh cycle 25 (addresses = don ? t care) t rp v v ih il ras# t ras open t chr t csr v v ih il v v oh ol cas# dq t rp t ras t rpc t csr t rpc t chr t cp v v ih il t wrp t wrh we# t wrp t wrh don ? t care undefined -5 -6 symbol min max min max units t rpc (fpm) 0 0 ns t rpc (edo) 5 5 ns t rps 90 105 ns t wrh (edo) 8 10 ns t wrp (edo) 8 10 ns t wrn (fpm) 10 10 ns t wrp (fpm) 10 10 ns self refresh cycle (addresses and oe# = don ? t care) v v ih il ras# t rass open v v ih il v v oh ol dq t rpc t chd t rps t rpc t rp t cp cas# we# v v ih il t wrh t wrp t wrh t wrp ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) note 1 t csr t cp note 2 ( ) ( ) ( ) ( ) note: 1. once t rass (min) is met and ras# remains low, the dram will enter self refresh mode. 2. once t rps is satisfied, a complete burst of all rows should be executed.
4, 8 meg x 64 dram sodimms micron technology, inc., reserves the right to change products or specifications without notice. dm83.p65 ? rev. 2/99 ?1999, micron technology, inc. 29 4, 8 meg x 64 dram sodimms hidden refresh cycle 20, 25 (we# = high) don ? t care undefined t clz t off open valid data open column row t cac t rac t aa t cah t asc t rah t asr t rad t ar t crp t rcd t rsh t ras t rc t rp t chr t ras dqx v v ioh iol v v ih il addr v v ih il v v ih il ras# v v ih il t oe t od oe# t ord casl#/cash# -5 -6 symbol min max min max units t off (fpm) 3 13 3 15 ns t off (edo) 0 12 0 15 ns t ord 0 0 ns t r a c 50 60 n s t rad (fpm) 13 15 ns t rad (edo) 9 12 ns t rah (edo) 9 10 ns t rah (fpm) 8 10 ns t ras 50 10,000 60 10,000 ns t rc (fpm) 90 110 ns t rc (edo) 84 104 ns t rcd (fpm) 18 20 ns t rcd (edo) 11 14 ns t rp 30 40 n s t rsh1315ns fast page mode and edo page mode timing parameters -5 -6 symbol min max min max units t a a 25 30 n s t ar (edo) 38 45 ns t ar (fpm) 40 45 ns t asc 0 0 ns t asr 0 0 ns t c a c 13 15 n s t cah 8 10 ns t chr (fpm) 15 15 ns t chr (edo) 8 10 ns t clz (fpm) 3 3 ns t clz (edo) 0 0 ns t crp 5 5 ns t od (fpm) 3 13 3 15 ns t od (edo) 0 12 0 15 ns t oe (edo) 12 15 ns t oe (fpm) 13 15 ns
4, 8 meg x 64 dram sodimms micron technology, inc., reserves the right to change products or specifications without notice. dm83.p65 ? rev. 2/99 ?1999, micron technology, inc. 30 4, 8 meg x 64 dram sodimms scl sda in sda out t low t su:sta t hd:sta t f t high t r t buf t dh t aa t su:sto t su:dat t hd:dat undefined spd eeprom symbol min max units t high 4 s t low 4.7 s t r1s t su:dat 250 ns t su:sta 4.7 s t su:sto 4.7 s spd eeprom timing parameters symbol min max units t aa 0.3 3.5 s t buf 4.7 s t dh 300 ns t f 300 ns t hd:dat 0 s t hd:sta 4 s
4, 8 meg x 64 dram sodimms micron technology, inc., reserves the right to change products or specifications without notice. dm83.p65 ? rev. 2/99 ?1999, micron technology, inc. 31 4, 8 meg x 64 dram sodimms .150 (3.80) max .043 (1.10) .035 (0.90) pin 1 2.667 (67.75) 2.656 (67.45) .071 (1.80) (2x) 2.386 (60.60) .0315 (.80) typ .130 (3.30) (2x) .024 (.60) typ .079 (2.00) r (2x) pin 143 (pin 144 on backside) front view .079 (2.00) .236 (6.00) 2.504 (63.60) .100 (2.55) .059 (1.50) typ 1.006 (25.55) 0.994 (25.25) .787 (20.00) typ .157 (4.00) 144-pin sodimm dg-7 (32mb) .150 (3.80) max .043 (1.10) .035 (0.90) 1.006 (25.55) 0.994 (25.25) pin 1 2.667 (67.75) 2.656 (67.45) .787 (20.00) typ .071 (1.80) (2x) 2.386 (60.60) .0315 (.80) typ .130 (3.30) (2x) .024 (.60) typ .079 (2.00) r (2x) pin 143 (pin 144 on backside) front view .079 (2.00) .236 (6.00) 2.504 (63.60) .100 (2.55) .059 (1.50) typ .157 (4.00) 144-pin sodimm dg-8 (64mb) note: all dimensions in inches (millimeters) max or typical where noted. min
4, 8 meg x 64 dram sodimms micron technology, inc., reserves the right to change products or specifications without notice. dm83.p65 ? rev. 2/99 ?1999, micron technology, inc. 32 4, 8 meg x 64 dram sodimms 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 e-mail: prodmktg@micronsemi.com, internet: http://www.micronsemi.com, customer comment line: 800-932-4992 micron is a registered trademark of micron technology, inc.

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